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? 2012 microchip technology inc. preliminary ds25156a-page 1 23LCV1024 device selection table features: ? spi-compatible bus interface: - 20 mhz clock rate - spi/sdi mode ? low-power cmos technology: - read current: 3 ma at 5.5v, 20 mhz - standby current: 4 ? a at +85c ? unlimited read and write cycles ? external battery backup support ? zero write time ? 128k x 8-bit organization: - 32-byte page ? byte, page and sequential mode for reads and writes ? high reliability ? temperature range supported: ? pb-free and rohs compliant, halogen free ? 8-lead soic, tssop and pdip packages pin function table description: the microchip technology inc. 23LCV1024 is a 1 mbit serial sram device. the memory is accessed via a simple serial peripheral interface (spi) compatible serial bus. the bus signals required are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input. additionally, sdi (serial dual inter- face) is supported if your application needs faster data rates. this device also supports unlimited reads and writes to the memory array, and supports data backup via an external battery/coin cell connected to v bat (pin 7). the 23LCV1024 is available in standard packages including 8-lead soic, pdip and advanced 8-lead tssop. package types (not to scale) part number v cc range dual i/o (sdi) battery backup max. clock frequency packages 23LCV1024 2.5-5.5v yes yes 20 mhz sn, st, p - industrial (i): -40 ? cto +85 ? c name function cs chip select input so/sio1 serial output/sdi pin vss ground si/sio0 serial input/sdi pin sck serial clock v bat external backup supply input vcc power supply cs so/sio1 nc vss vcc v bat sck si/sio0 1 2 3 4 8 7 6 5 soic/tssop/pdip 1 mbit spi serial sram with battery backup and sdi interface
23LCV1024 ds25156a-page 2 preliminary ? 2012 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.3v to v cc +0.3v storage temperature ............................................................................................................ ...................-65c to +150c ambient temperature under bias ................................................................................................. ..............-40c to +85c table 1-1: dc characteristics ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for an extended period of time may affect device reliability. dc characteristics industrial (i): t a = -40c to +85c param. no. sym. characteristic min. typ. (1) max. units test conditions d001 v cc supply voltage 2.5 ? 5.5 v 23LCV1024 d002 v ih high-level input voltage .7 v cc ?v cc +0.3 v d003 v il low-level input voltage -0.3 ? 0.10xv cc v 23LCV1024 d004 v ol low-level output voltage ??0.2vi ol = 1 ma d005 v oh high-level output voltage v cc -0.5 ? ? v i oh = -400 ? a d006 i li input leakage current ?? 1 ? acs = v cc , v in = v ss or v cc d007 i lo output leakage current ?? 1 ? acs = v cc , v out = v ss or v cc d008 i cc read operating current ? 3 10 ma f clk = 20 mhz; so = o, 5.5v d009 i ccs standby current ? 4 10 ? acs = v cc = 5.5v, inputs tied to v cc or v ss d010 c int input capacitance ? ? 7 pf v cc = 0v, f = 1 mhz, ta = 25c ( note 1 ) d011 v dr ram data retention voltage ?1.0 ? v ( note 2 ) d012 vtrip v bat change over 1.6 1.8 2.0 v typical at ta = 25c ( note 1 ) d013 v bat v bat voltage range 1.4 ? 3.6 v ( note 1 ) d014 ibat v bat current ? 1 ? ? a typical at 2.5v, ta = 25c ( note 1 ) note 1: this parameter is periodically sampled and not 100% tested. typical measurements taken at room temperature (25c). 2: this is the limit to which v dd can be lowered without losing ram data. this parameter is periodically sampled and not 100% tested.
? 2012 microchip technology inc. preliminary ds25156a-page 3 23LCV1024 table 1-3: ac test conditions table 1-2: ac characteristics ac characteristics industrial (i): t a = -40c to +85c param. no. sym. characteristic min. max. units test conditions 1f clk clock frequency ? 20 mhz 2t css cs setup time 25 ? ns 3t csh cs hold time 50 ? ns 4t csd cs disable time 25 ? ns 5 tsu data setup time 10 ? ns 6t hd data hold time 10 ? ns 7t r clk rise time ? 20 ns note 1 8t f clk fall time ? 20 ns note 1 9t hi clock high time 25 ? ns 10 t lo clock low time 25 ? ns 11 t cld clock delay time 25 ? ns 12 t v output valid from clock low ?25ns 13 t ho output hold time 0 ? ns note 1 14 t dis output disable time ?20ns note 1: this parameter is periodically sampled and not 100% tested. ac waveform: input pulse level 0.1 v cc to 0.9 v cc input rise/fall time 5 ns operating temperature -40c to +85c c l = 30 pf ? timing measurement reference level: input 0.5 v cc output 0.5 v cc
23LCV1024 ds25156a-page 4 preliminary ? 2012 microchip technology inc. figure 1-1: serial input timing (spi mode) figure 1-2: serial output timing (spi mode) cs sck si so 6 5 8 7 11 3 lsb in msb in high-impedance 2 4 cs sck so 10 9 12 msb out lsb out 3 14 don?t care si 13
? 2012 microchip technology inc. preliminary ds25156a-page 5 23LCV1024 2.0 functional description 2.1 principles of operation the 23LCV1024 is an 1 mbit serial sram designed to interface directly with the serial peripheral interface (spi) port of many of today?s popular microcontroller families, including microchip?s pic ? microcontrollers. it may also interface with microcontrollers that do not have a built-in spi port by using discrete i/o lines programmed properly in firmware to match the spi protocol. in addition, the 23LCV1024 is also capable of operating in sdi (or dual spi) mode. the 23LCV1024 contains an 8-bit instruction register. the device is accessed via the si pin, with data being clocked in on the rising edge of sck. the cs pin must be low for the entire operation. table 2-1 contains a list of the possible instruction bytes and format for device operation. all instructions, addresses and data are transferred msb first, lsb last. 2.2 modes of operation the 23LCV1024 has three modes of operation that are selected by setting bits 7 and 6 in the mode register. the modes of operation are byte, page and burst. byte operation ? is selected when bits 7 and 6 in the mode register are set to 00 . in this mode, the read/ write operations are limited to only one byte. the command followed by the 24-bit address is clocked into the device and the data to/from the device is transferred on the next eight clocks ( figure 2-1 , figure 2-2 ). page operation ? is selected when bits 7 and 6 in the mode register are set to 10 . the 23LCV1024 has 4096 pages of 32 bytes. in this mode, the read and write oper- ations are limited to within the addressed page (the address is automatically incremented internally). if the data being read or written reaches the page boundary, then the internal address counter will increment to the start of the page ( figure 2-3 , figure 2-4 ). sequential operation ? is selected when bits 7 and 6 in the mode register are set to 01 . sequential opera- tion allows the entire array to be written to and read from. the internal address counter is automatically incremented and page boundaries are ignored. when the internal address counter reaches the end of the array, the address counter will roll over to 0x00000 ( figure 2-5 , figure 2-6 ). 2.3 read sequence the device is selected by pulling cs low. the 8-bit read instruction is transmitted to the 23LCV1024 followed by the 24-bit address, with the first seven msb?s of the address being a ?don?t care? bit. after the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. if operating in sequential mode, the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. the internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address is reached (1ffffh), the address counter rolls over to address 00000h, allowing the read cycle to be continued indefinitely. the read operation is terminated by raising the cs pin. 2.4 write sequence prior to any attempt to write data to the 23LCV1024, the device must be selected by bringing cs low. once the device is selected, the write command can be started by issuing a write instruction, followed by the 24-bit address, with the first seven msb?s of the address being a ?don?t care? bit, and then the data to be written. a write is terminated by the cs being brought high. if operating in page mode, after the initial data byte is shifted in, additional bytes can be shifted into the device. the address pointer is automatically incremented. this operation can continue for the entire page (32 bytes) before data will start to be overwritten. if operating in sequential mode, after the initial data byte is shifted in, additional bytes can be clocked into the device. the internal address pointer is automati- cally incremented. when the address pointer reaches the highest address (1ffffh), the address counter rolls over to (00000h). this allows the operation to continue indefinitely, however, previous data will be overwritten.
23LCV1024 ds25156a-page 6 preliminary ? 2012 microchip technology inc. figure 2-1: byte read sequence (spi mode) figure 2-2: byte write sequence (spi mode) table 2-1: instruction set instruction name instruction format hex code description read 0000 0011 0x03 read data from memory array beginning at selected address write 0000 0010 0x02 write data to memory array beginning at selected address edio 0011 1011 0x3b enter dual i/o access rstio 1111 1111 0xff reset dual i/o access rdmr 0000 0101 0x05 read mode register wrmr 0000 0001 0x01 write mode register so si sck cs 0 234567891011 29303132333435363738 39 1 01 0 0 0 0 01 23 22 21 20 210 76543210 instruction 24-bit address data out high-impedance so si cs 9 1011 29303132333435363738 39 00 0 0 0 0 01 23 22 21 20 210 76543210 instruction 24-bit address data byte high-impedance sck 0 234567 1 8
? 2012 microchip technology inc. preliminary ds25156a-page 7 23LCV1024 figure 2-3: page read sequence (spi mode) figure 2-4: page write sequence (spi mode) 76543210 page x, word y si cs 9 1011 29303132333435363738 39 23 22 21 20 210 24-bit address sck 0 234567 1 8 so cs 76543210 page x, word 0 sck 40 42 43 44 45 46 47 41 76543210 page x, word 31 76543210 page x, word y+1 page x, word y so high-impedance si 01 0 0 0 0 01 instruction si cs 9 1011 29303132333435363738 39 23 22 21 20 210 76543210 24-bit address sck 0 234567 18 cs si 76543210 page x, word 0 76543210 page x, word 31 76543210 page x, word y+1 page x, word y page x, word y sck 40 42 43 44 45 46 47 41 00 0 0 0 0 01 instruction
23LCV1024 ds25156a-page 8 preliminary ? 2012 microchip technology inc. figure 2-5: sequential re ad sequence (spi mode) si cs 9 1011 29303132333435363738 39 23 22 21 20 210 76543210 instruction 24-bit address page x, word y sck 0 234567 18 so cs 76543210 page x+1, word 1 sck 76543210 page x+1, word 0 76543210 page x, word 31 so cs 76543210 page x+n, word 31 sck 76543210 page x+n, word 1 76543210 page x+1, word 31 so si si 01 0 0 0 0 01
? 2012 microchip technology inc. preliminary ds25156a-page 9 23LCV1024 figure 2-6: sequential write sequence (spi mode) si cs 9 1011 29303132333435363738 39 00 0 0 0 0 01 23 22 21 20 210 76543210 instruction 24-bit address data byte 1 sck 0 234567 18 si cs 49 50 51 54 55 76543210 data byte n sck 40 42 43 44 45 46 47 41 48 76543210 data byte 3 76543210 data byte 2 52 53
23LCV1024 ds25156a-page 10 preliminary ? 2012 microchip technology inc. 2.5 read mode register instruction ( rdmr ) the read mode register instruction ( rdmr ) provides access to the mode register. the mode register may be read at any time. the mode register is formatted as follows: table 2-2: mode register the mode bits indicate the operating mode of the sram. the possible modes of operation are: 0 0 = byte mode 1 0 = page mode 0 1 = sequential mode (default operation) 1 1 = reserved bits 0 through 5 are reserved and should always be set to ? 0 ?. see figure 2-7 for the rdmr timing sequence. figure 2-7: read mode regi ster timing sequence ( rdmr ) 76543210 w/r w/r ? ? ? ? ? ? mode mode 00000 0 w/r = writable/readable so si cs 91011 12131415 11 0 0 0 0 00 7654 2 10 instruction data from mode register high-impedance sck 0 234567 1 8 3
? 2012 microchip technology inc. preliminary ds25156a-page 11 23LCV1024 2.6 write mode register instruction ( wrmr ) the write mode register instruction ( wrmr ) allows the user to write to the bits in the mode register as shown in table 2-2 . this allows for setting of the device operating mode. several of the bits in the mode register must be cleared to ? 0 ?. see figure 2-8 for the wrmr timing sequence. figure 2-8: write mode regi ster timing sequence ( wrmr ) 2.7 power-on state the 23LCV1024 powers on in the following state: ? the device is in low-power standby mode (cs = 1 ) ? a high-to-low-level transition on cs is required to enter active state so si cs 91011 12131415 01 0 0 0 0 00 7654 210 instruction data to mode register high-impedance sck 0 234567 18 3
23LCV1024 ds25156a-page 12 preliminary ? 2012 microchip technology inc. 3.0 pin descriptions the descriptions of the pins are listed in tab l e 3 - 1 . table 3-1: pin function table 3.1 chip select (cs ) a low level on this pin selects the device. a high level deselects the device and forces it into standby mode. when the device is deselected, so goes to the high- impedance state, allowing multiple parts to share the same spi bus. after power-up, a low level on cs is required, prior to any sequence being initiated. 3.2 serial output (so) the so pin is used to transfer data out of the 23LCV1024. during a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 3.3 serial input (si) the si pin is used to transfer data into the device. it receives instructions, addresses, and data. data is latched on the rising edge of the serial clock. 3.4 serial dual interface pins(sio0, sio1) the sio0 and sio1 pins are used for sdi mode of operation. functionality of these i/o pins is shared with so and si. 3.5 serial clock (sck) the sck is used to synchronize the communication between a master and the 23LCV1024. instructions, addresses or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin is updated after the falling edge of the clock input. 3.6 vbat supply input the v bat pin is used as an input for external backup supply to maintain sram data when v cc is below the vtrip point. if the v bat function is not being used it is recommended to connect this pin to v ss . 3.7 spi and sdi pin designations name soic/ pdip tssop function cs 1 chip select input so/sio1 2 serial data output/sdi pin nc 3 no connect v ss 4ground si/sio0 5 serial data input/sdi pin sck 6 serial clock input v bat 7 external backup supply v cc 8 power supply cs sio1 nc vss vcc v bat sck sio0 1 2 3 4 8 7 6 5 sdi mode: cs so nc vss vcc v bat sck si 1 2 3 4 8 7 6 5 spi mode:
? 2012 microchip technology inc. preliminary ds25156a-page 13 23LCV1024 4.0 dual serial mode the 23LCV1024 also supports sdi (serial dual) mode of operation when used with compatible master devices. as a convention for sdi mode of operation, two bits are entered per clock using the sio0 and sio1 pins. bits are clocked msb first. 4.1 dual interface mode the 23LCV1024 supports sdi (serial dual) mode of operation. to enter sdi mode the edio command must be clocked in ( figure 4-1 ). it should be noted that if the mcu resets before the sram, the user will need to determine the serial mode of operation of the sram and reset it accordingly. byte read and write sequence in sdi mode is shown in figure 4-2 and figure 4-3 . figure 4-1: enter sdi mode (edio) from spi mode figure 4-2: byte read mode sdi sck 0 234567 1 si high-impedance so cs 00 0111 1 1 note: page and sequential mode are similar in that additional bytes can be clocked out before cs is brought high. note: the first byte read after the address will be a dummy byte. cs 14 15 16 17 18 19 20 21 22 23 02 3 45 6 1 420 22 20 18 531 23 21 19 24-bit address instruction dummy byte 642 0 753 1 data out sck sio0 sio1 1 0 0 0 00 0 1 13
23LCV1024 ds25156a-page 14 preliminary ? 2012 microchip technology inc. figure 4-3: byte write mode sdi 4.2 exit sdi mode to exit from sdi mode, the rstio command must be issued. the command must be entered in the current device configuration see ( figure 4-4 ) figure 4-4: reset sdi mode (rstio) ? from sdi mode note: page and sequential mode are similar in that additional bytes can be clocked in before cs is brought high. cs 13 14 15 16 17 18 19 0234 5 6 1 420 22 20 18 531 23 21 19 24-bit address instruction data in 642 0 753 1 sck sio1 0 0 0 0 00 0 1 sio0 sck 0 2 3 1 sio0 cs 111 1 sio1 111 1
? 2012 microchip technology inc. preliminary ds25156a-page 15 23LCV1024 5.0 vbat the 23LCV1024 features an internal switch that will maintain the sram contents. in the event that the v cc supply is not available, the voltage applied to the v bat pin serves as the backup supply. the v bat trip point is the point at which the internal switch operates the device from the vbat supply and is typically 1.8v (vtrip specification d012). when v cc falls below the vtrip point the system will continue to maintain the sram contents. the following conditions apply: supply condition read/write access powered by vcc < vtrip, vcc < vbat no v bat vcc > vtrip, vcc < vbat yes v cc vcc > vtrip, vcc > vbat yes v cc
23LCV1024 ds25156a-page 16 preliminary ? 2012 microchip technology inc. 6.0 packaging information 6.1 package marking information 8-lead soic (3.90 mm) xxxxyyww xxxxxxxt nnn example: sn 0528 23lcvbi 1l7 legend: xx...x part number or part number code t temperature (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 8-lead tssop example: xxxx tyww nnn 3lvb i837 1l7 8-lead pdip (300 mil) example xxxxxxxx xxxxxnnn yyww 23lcvb i/p 1l7 0528 3 e
? 2012 microchip technology inc. preliminary ds25156a-page 17 23LCV1024 n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c
23LCV1024 ds25156a-page 18 preliminary ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012 microchip technology inc. preliminary ds25156a-page 19 23LCV1024 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
23LCV1024 ds25156a-page 20 preliminary ? 2012 microchip technology inc.
? 2012 microchip technology inc. preliminary ds25156a-page 21 23LCV1024 d n e e1 note 1 12 b e c a a1 a2 l1 l
23LCV1024 ds25156a-page 22 preliminary ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012 microchip technology inc. preliminary ds25156a-page 23 23LCV1024 appendix a: revision history revision a (09/2012) initial release.
23LCV1024 ds25156a-page 24 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds25156a-page 25 23LCV1024 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
23LCV1024 ds25156a-page 26 preliminary ? 2012 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds25156a 23LCV1024 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2012 microchip technology inc. preliminary ds25156a-page 27 23LCV1024 product identification system to order or obtain information, e.g., on pr icing or delivery, refer to the factory or the listed sales office. not all possible ordering options are shown below. . part no. x /xx package tape & reel device device: 23LCV1024= 1 mbit, 2.5 - 5.5v, spi serial sram tape & reel: blank = t= standard packaging (tube) ta p e & r e e l temperature range: i= -40 ? c to+85 ? c package: sn = st = p= plastic soic (3.90 mm body), 8-lead plastic tssop (4.4 mm body), 8-lead plastic pdip (300 mil body), 8-lead examples: a) 23LCV1024-i/st = 1 mbit, 2.5 - 5.5v serial sram, industrial temp., tssop package b) 23LCV1024-i/sn = 1 mbit, 2.5 - 5.5v serial sram, industrial temp., soic package c) 23LCV1024-i/p = 1 mbit, 2.5 - 5.5v serial sram, industrial temp., pdip package ? x tem p range
23LCV1024 ds25156a-page 28 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds25156a-page 29 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620765999 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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